Novel Hardware Implementation for Fast Address Lookups

The major bottleneck in the performance of routers is the address lookup for determining the next hop address. The problem of determining the next hop is made more complicated by the fact that routers store variable length prefixes in the forwarding tables. This paper describes a new hardware algorithm that gives a fast and efficient solution for address lookups. As implemented in the forwarding engine of a network processor or router, an overhead of a small on-chip SRAM and some additional circuitry is required. Forwarding table search is performed only on this SRAM, and subsequently only one DRAM access is needed for output port assignment. In our implementation, the throughput of the forwarding engine implemented is limited by the random access time of the off-chip DRAM. This means that a lookup is performed every 64ns giving over 15 million lookups per second. The throughput can be made much higher by using multiple DRAMs. The amount of on-chip SRAM is quite small and around 40KB of SRAM memory is required for a routing table of over 40,000 entries. Keywords— Address Lookup, Forwarding Engine, Network Processor